The invention relates to an electrically erasable programmable read only memory (E.sup.2 PROM) formed on a semiconductor substrate.
E.sup.2 PROMs are integrated circuits and are typically manufactured in NMOS technology. Most of the active devices of an E.sup.2 PROM are NMOS transistors formed by heavily doped N-type (N+) regions separated by a lightly doped P-type (P-) region, all in a semiconductor substrate. The P- region forms the channel between the N+ regions. The conductivity between the N+ regions through the channel is controlled by electrical signals on a gate electrode in close proximity over, but electronically isolated from, the channel.
E.sup.2 PROMs are organized in a rectangular array of memory cells formed in a semiconductor substrate with each cell in the array storing a single bit of information. The cells are addressed by their row and column locations in the array. Each cell is a circuit including transistors coupling a bit line to ground. The transistors are controlled by signals on word and program control lines which supply predetermined voltages to the gates of the transistors. The transistor controlled by the program control line is a stacked gate transistor including a floating polysilicon gate below a control gate. The stacked gate transistor will conduct if the floating gate is uncharged and will not conduct if the floating gate is charged.
A given cell in the array is read by the following procedure. First the bit line connected to the cell is biased positively while the word and program lines intersecting the cell are biased to predetermined voltages. A current sensing amplifier provides a digital output corresponding to the flow of current from the bit line through the cell to ground. Current will flow if the floating gate is uncharged (erased), which is the logic 1 state, and will not flow if the cell is charged (programmed), which is the logic 0 state.
The floating gate in a given cell is charged (programmed) by electrons tunneling through a special dielectric region separating an N+ region in the substrate, which is grounded, from the floating polysilicon gate. This tunneling is induced by biasing the control gate to a high voltage (about +20 volts), which brings the floating gate to a high voltage due to capacitive coupling between the control gate and the floating gate. The floating gate is discharged (erased) by raising the N+ region to a high voltage and grounding the control gate.
An array of E.sup.2 PROM memory cells includes an N+ region in the substrate interconnecting a column of cells to ground. During the program/erase operations, DC current is drawn through the N+ region. Because of this current an external high voltage supply is required for the program/erase operations. In many applications, only a single, low voltage power supply, typically 5 volts, is available, so that the above-described E.sup.2 PROM cell is of limited utility. Additionally, the N+ diffusion region interconnecting the column of cells prevents the cells from being completely electrically isolated from each other and causes disturbance of neighboring cells during a program/erase operation for a given cell.
Recently, E.sup.2 PROM cells interconnected by a metal bit read line instead of a common N+ diffusion region have been developed. Each cell includes an isolated N+ region interconnected with another metal line, a bit write line, instead of the common N+ diffusion of the above-described cells. By allowing the metal bit read line to float electrically and using the metal bit write line to apply position voltages to the N+ regions of the memory cell, the floating gate is charged and discharged. Little DC current is drawn. This approach allows the use of on-chip circuitry to generate the high voltage required for the program/erase operations and allows the cell to function with only an external five volt supply interconnected thereto. While this cell is advantageous over other prior art memory cells, its area on a semiconductor substrate has not been minimized.